1. Field of the Invention
The invention relates to a method of positioning a semiconductor integrated circuit onto a semiconductor substrate, and also to an apparatus of carrying out the method. The invention relates more particularly to a method of positioning a semiconductor integrated circuit device including both analog and digital circuits therein, and also to an apparatus of carrying out the method.
2. Description of the Related Art
When a semiconductor integrated circuit including analog and digital circuits therein is arranged on a semiconductor substrate, structure and layout for analog and digital circuits are separately designed, because individual semiconductor integrated circuit devices have different device characteristics and uses. A semiconductor integrated circuit device is designed under hierarchy design, and the analog and digital circuits are connected to each other in top hierarchy. That is, a design of an interface between them is accomplished at top hierarchy. Conventional steps of designing a semiconductor integrated circuit device including analog and digital circuits are explained hereinbelow with reference to FIGS. 1 and 2A to 2C.
With reference to FIG. 1, analog and digital circuits and are designed in step 51. Then, interfaces for the analog and digital circuits designed in step 51 are designed at top hierarchy in step 52. Then, in step 53, a layout 61 (see FIG. 2A) of the analog circuit is designed based on connection data of the analog circuit, and a layout 62 (see FIG. 2A) of the digital circuit is also designed based on connection data of the digital data. Data about the thus designed layouts 61 and 62 of the analog and digital circuits are stored in layout data storing regions 55 and 51, respectively. Then, in step 54, hard macros 63 and 64, illustrated in FIG. 2B, for the analog and digital circuits are designed based on data of the layouts 61 and 62 of the analog and digital circuits. The thus designed hard macros 63 and 64 of the analog and digital circuits are stored in a region 56 in step 55. Finally, in step 56, interfaces for the analog and digital circuits are designed based on both connection data of top hierarchy 65 having been designed in step 52 and the hard macros 63, 64 of the analog and digital circuits having been stored in the layout-designing device 56 in step 55. The thus designed interfaces of the analog and digital circuits are stored in a layout-storing region 57.
By carrying out the above-mentioned steps. it is possible to design a semiconductor integrated circuit including different design rules. However, it is necessary to establish the hard macros 63 and 64 for the analog and digital circuits, and hence the interfaces are designed for the analog and digital circuits at the top hierarchy. Thus, it is necessary to have the layout region 65 for the interfaces, as illustrated in FIG. 2C, and it is further necessary to examine the connection between the analog and digital circuits to assure the connection therebetween.
For example, Japanese Unexamined Patent Publication No. 6-268064 has suggested a method of designing a layout of a semiconductor integrated circuit device. FIG. 3 illustrates the flowchart of this method, which is almost the same as the flowchart illustrated in FIG. 1, but is different only in that there is formed a region 77 for storing a hard macro model, and the thus stored hard macro model is used for designing hard macros of analog and digital circuits in step 54.
Specifically, hard macro models 87 and 88 for the analog and digital circuits are in advance formed in order to make it easy to establish hard macros for the analog and digital circuits, as illustrated in FIG. 4A. After analog and digital circuits 81 and 82 (see FIG. 4A) have been positioned, data about positioning of interface terminals is replaced with data 83 and 84 about positioning of terminals of the hard macro models 87 and 88, thereby the hard macros for the analog and digital circuits are established. In addition, even in the above-mentioned method, it is necessary to prepare a layout region 85 for interfaces, and it is also necessary to make examination on the connection between the analog and digital circuits 81 and 82 to assure the connection therebetween.
The above-mentioned method has problems as follows. The first one is that when LSI including analog and digital circuits, which employs Bi-CMOS process, is to be fabricated, it would take much time to examine a connection between the analog and digital circuits for assurance thereof. The reason is as follows. Since the analog and digital circuits in LSI employing Bi-CMOS process have different device characteristics and uses, they have different design rules, and hence, structure and layout of them are separately designed. Hence, it is necessary to make examination on connection between the analog and digital circuits.
The second problem is difficulty in applying a computer-aided design (CAD) tool to the method. The reason is as follows. Since the analog and digital circuits have different device characteristics and uses, different design rules are applied to them. Hence, it is unavoidable that conditions for applying CAD tool to the method become complicated.
The third problem is that it is difficult to increase an area occupied by a chip of LSI including analog and digital circuits. The reason is as follows. Even in accordance with the above-mentioned method suggested in Japanese Unexamined Patent Publication No. 6-268064, it is possible to establish hard macros for analog and digital circuits, and design wiring layout. However, it is necessary to secure an area for wirings to be used only for connecting the analog and digital circuits to each other, which decreases an area for LSI chip.